This invention relates generally to a reference charge generator, a method for providing a reference charge from a reference charge generator, a method of operating a reference charge generator and a DRAM memory.
The reduction in memory cell and other circuit size required for high density dynamic random access memories (DRAMs) and other circuitry is a continuing goal in semiconductor fabrication. Implementing electric circuits involves connecting isolated devices through specific electric paths. When fabricating silicon and other material into integrated circuits, it is necessary to isolate devices built into the substrate from one another. Electrical isolation of devices as circuit density increases is a continuing challenge.
One method of isolating devices involves the formation of a semi-recessed or fully recessed oxide in the non-active (or field) area of the substrate. These regions are typically termed as xe2x80x9cfield oxidexe2x80x9d and are formed by LOCal Oxidation of exposed Silicon, commonly known as LOCOS. One approach in forming such oxide is to cover the active regions with layer of silicon nitride that prevents oxidation from occurring therebeneath. A thin intervening layer of a sacrificial pad oxide is provided intermediate the silicon substrate and nitride layer to alleviate stress and to protect the substrate from damage during subsequent removal of the nitride layer. The unmasked or exposed field regions of the substrate are then subjected to a wet (H2O) oxidation, typically at atmospheric pressure and at temperatures of around 1000xc2x0 C., for two to four hours. This results in field oxide growth where there is no masking nitride.
However, LOCOS structures do not necessarily lend themselves to progressively smaller feature sizes and/or increased densities. This is discussed to some extent in U.S. Pat. No. 5,700,733, filed on Jun. 27, 1995, entitled xe2x80x9cSemiconductor Processing Methods Of Forming Field Oxide Regions On A Semiconductor Substratexe2x80x9d and issued to M. Manning, the disclosure of which is incorporated herein by reference for its teachings and which is assigned to the assignee of this patent document.
The above-noted patent presents a technique for using shallow trench isolation (STI) to realize a compact and robust DRAM cell having an area of 8F2. However, increasing demand for yet more compact and robust memory designs has continued to drive demand for even smaller cell areas.
Another alternative isolation technique uses an isolation gate structure formed between adjacent memory cells. The gate structure is biased to greatly reduce the number of mobile charge carriers in the semiconducting material beneath the isolation gate structure. This architecture has the advantage of providing extremely compact memory cells having an effective area of about 6F2 (compared, for example, to an area of about 8F2 for the LOCOS structures described above), resulting in a compact memory device.
As operating voltages are reduced to try to reduce overall system power requirements, bitline precharge circuitry may have to operate at voltages comparable to power supply voltages, i.e., at VCC or at ground. This arises because transistor threshold (i.e., turn-on) voltages tend to be order-of-magnitude comparable to the voltages now being used for power supply voltages. In turn, this necessitates techniques for generating reference charge magnitudes comparable to half of the amount of charge normally employed to store data in DRAM memory cells.
In a first aspect, the present invention provides a reference charge generator for a memory. The reference charge generator includes a first switch having a control terminal and first and second load electrodes. The first load electrode is coupled to a bitline and the second load electrode is coupled to a first node. The reference charge generator also includes a first reference capacitor having a capacitance CREF. The first reference capacitor has a non-planar capacitor configuration and has first and second terminals. The first terminal is coupled to the first node and the second terminal is coupled to a common node. The reference charge generator further includes a second reference capacitor having a capacitance CREF. The second reference capacitor has a non-planar capacitor configuration and has first and second terminals. The second terminal is coupled to the commom node. The reference charge generator is configured to (i) couple at least one of the first and second reference capacitors to a voltage V, (ii) the at least one of the first and second capacitors from the voltage V, (iii) store a first charge Q1 in at least one of the first and second reference capacitors and (iv) couple a reference charge QREF from at least one of the first and second reference capacitors to the bitline, where QREF=CREFV/2.
In another aspect, the present invention includes a reference charge generator for providing reference signals in a memory. The reference charge generator includes a first reference capacitor having capacitance CREF. The first reference capacitor has a non-planar capacitor configuration and has first and second terminals. The second terminal is coupled to a common node. The reference charge generator also includes a second reference capacitor having capacitance CREF. The second reference capacitor has a non-planar capacitor configuration and has first and second terminals. The second terminal is coupled to the common node. The reference charge generator further includes a first switch having a control electrode and first and second load electrodes. The first load electrode is coupled to a bitline, and the second load electrode is coupled to a first node and to the first terminal of the first reference capacitor. The reference charge generator additionally includes a second switch having a control electrode and first and second load electrodes. The first load electrode of the second switch is coupled to the first node. The second load electrode of the second switch is coupled to a second node and to the first terminal of the second capacitor. The reference charge generator also includes a third switch having a control electrode and first and second load electrodes. The first load electrode of the third switch is coupled to the second node and the second load electrode is coupled to a power supply conductor.
In a further aspect, the present invention includes a method for providing a reference charge from a reference charge generator. The method includes coupling a pair of non-planar reference capacitors each having a capacitance CREF between a power supply voltage V and ground to provide a first stored charge QREF, where QREF=CREFV/2, decoupling the pair of reference capacitors from the power supply voltage V and coupling the first stored charge QREF=from the pair of reference capacitors to a bitline.